This thorough revision of CMOS VLSI Design provides students with all the key concepts they need for a course in CMOS VLSI Design.

• Revised introduction of designing schematics and layout for simple CMOS circuits.
• Updated discussion of non-ideal transistor behaviors and their design implications.
• Simplified RC delay models and integration of Logical Effort, as a means for discussing fast circuits and estimating delay.
• Greater attention to power and leakage.
• Expanded coverage of interconnect.
• New chapter on SPICE simulation and process characterization.
• Greater coverage of high-performance domino circuits and circuit pitfalls.
• Detailed coverage of modern clocking and latching techniques.
• Expanded chapters on datapath and memory circuits.
• Unified treatment of high-performance CMOS adders comparing techniques.
• Real-world horror stories of chips "gone bad" and the lessons they provide today's designers.
• Historical Perspective and Pitfall sections link the theory in the text to what is happening (and going wrong) behind industry doors.
• Examples drawing on modern process technology.
• New appendices on Verilog and VHDL - look at from a practical perspective.
• Two-color illustrations for improved readability.
• Full-color inside cover quick reference guide to MOSIS layout design rules.
• Improved exercises (about 20 per chapter) including many easier problems suitable for weekly problem sets.